This invention is in the field of integrated circuit manufacture. Embodiments of this invention are more specifically directed to the formation of capacitors in memory devices such as ferroelectric memories.
Conventional metal-oxide-semiconductor (MOS) and complementary MOS (CMOS) logic and memory devices are prevalent in modern electronic devices and systems, as they provide an excellent combination of fast switching times and low power dissipation, along with their high density and suitability for large-scale integration. As is fundamental in the art, however, those devices are essentially volatile, in that logic and memory circuits constructed according to these technologies do not retain their data states upon removal of bias power. Especially in mobile and miniature systems, the ability to store memory and logic states in a non-volatile fashion is very desirable. As a result, various technologies for constructing non-volatile devices have been developed in recent years.
A recently developed technology for realizing non-volatile solid-state memory devices involves the construction of capacitors in which the dielectric material is a polarizable ferroelectric material, such as lead-zirconium-titanate (PZT) or strontium-bismuth-tantalate (SBT), rather than silicon dioxide or silicon nitride as typically used in non-ferroelectric capacitors. Hysteresis in the charge-vs.-voltage (Q-V) characteristic, based on the polarization state of the ferroelectric material, enables the non-volatile storage of binary states in those capacitors. In contrast, conventional MOS capacitors lose their stored charge on power-down of the device. It has been observed that ferroelectric capacitors can be constructed by processes that are largely compatible with modern CMOS integrated circuits.
Non-volatile solid-state read/write random access memory (RAM) devices based on ferroelectric capacitors, such memory devices commonly referred to as “ferroelectric RAM”, or “FeRAM”, or “FRAM” devices, have been implemented in many electronic systems, particularly portable electronic devices and systems. FRAMs are especially attractive in implantable medical devices, such as pacemakers and defibrillators. Various memory cell architectures including ferroelectric capacitors are known in the art, including the well-known 2T2C (two transistor, two capacitor) cells. Another type of FRAM cell is based on the well-known “6T” CMOS static RAM cell, which operates as an SRAM cell during normal operation, but in which ferroelectric capacitors coupled to each storage node can be programmed with the stored data state to preserve memory contents in non-volatile fashion. Ferroelectric capacitors are also implemented in some integrated circuits as programmable analog capacitors.
FIG. 1 illustrates the construction of an example of a portion of an integrated circuit including a portion of a ferroelectric random access memory (FRAM). In this example, ferroelectric capacitor 15 and metal-oxide-semiconductor (MOS) transistor 17 are disposed at or near a semiconducting surface of a semiconductor substrate, although capacitor 15 and transistor 17 may instead be formed at the surface of a semiconductor layer that overlies an insulator layer, such as according to a silicon-on-insulator (SOI) technology as known in the art. In the example of FIG. 1, isolation dielectric structures 11, gate electrode 16, and n-type source/drain regions 14 are disposed at or near the surface of substrate 10, in the conventional manner for MOS integrated circuits. N-channel MOS transistor 17 in the example of FIG. 1 includes n-type source/drain regions 14 at the surface of p-type substrate 10 (or of a p-type “well” formed into substrate 10, as the case may be), with gate electrode 16 overlying a channel region between source/drain regions 14, and separated from the channel region by a gate dielectric, as conventional. Interlevel dielectric 12 is disposed over transistor 17, with conductive plug 13 disposed in a contact opening through interlevel dielectric 12 to provide a conductive connection between one of source/drain regions 14 of transistor 17 and lower plate 20a of ferroelectric capacitor 15.
In the example of FIG. 1, ferroelectric capacitor 15 is formed of a ferroelectric “sandwich” stack of conductive plates 20a, 20b, between which ferroelectric material 22 is disposed. Lower plate 20a is formed at a location overlying conductive plug 13, as shown in FIG. 2, so as to be in electrical contact with the underlying source/drain region 14 by way of conductive plug 13. Conductive plates 20a, 20b are typically formed of the same conductive material or materials as one another, for purposes of symmetry, simplicity of the manufacturing flow, and improved ferroelectric polarization performance. As mentioned above, ferroelectric material 22 in this conventional transistor 15 is typically lead-zirconium-titanate (PZT) or strontium-bismuth-tantalate (SBT), deposited by way of metalorganic chemical vapor deposition. Ferroelectric material 22 in capacitor 15 is desirably as thin as practicable, for purposes of electrical performance (e.g., capacitance), and for consistency with the deep submicron features used to realize modern integrated circuits.
Lower conductive plate 20a and upper conductive plate 20b are formed from one or more layers of conductive metals, metal oxides, and the like. A typical construction of lower conductive plate 20a is a stack of a diffusion barrier layer in contact with conductive plug 13 and a layer of a noble metal (e.g., Ru, Pt, Ir, Rh, Pt, Pd, Au) or metal oxide (e.g., RuOx, IrOx, PdOx, SrRuO3) overlying the barrier layer and in contact with the ferroelectric material 22. As described in commonly assigned U.S. Pat. No. 6,656,748, incorporated herein by reference, in capacitors in which PZT serves as ferroelectric material 22, sputter deposited iridium (Ir) is a preferred material for the portion of lower conductive plate 20a that is in direct contact with the PZT. As mentioned above, upper conductive plate 20b is typically formed of the same materials as lower conductive plate 20a, deposited in the reverse order (e.g., with iridium in contact with the top surface of PZT ferroelectric material 22).
As well-known in the manufacture of integrated circuits, the adhesion between adjacent layers in the integrated circuit is an important factor in the manufacturing yield and also in the reliability of the integrated circuits. Ensuring good adhesion between materials can be a particular challenge in complex structures such as ferroelectric capacitor 15 of FIG. 1, because of the dissimilarity of materials involved in the structure. It has been observed that delamination of PZT ferroelectric material 22 from the top surface of lower conductive plate 20a can be a particular problem in the manufacture of FRAMs.
By way of further background, U.S. Pat. No. 6,730,354, incorporated herein by reference, describes the formation of a PZT film by way of metalorganic chemical vapor deposition (MOCVD).